1. Field of the Invention
The present invention is directed to a solid-state relay, and more particularly to a solid-state relay having a pair of LDMOSFETs of which drains define output terminals for connection with a load to be controlled by the relay.
2. Description of the Prior Art
Solid-state relays have been widely utilized in place of mechanical relays in view of many advantages including miniaturized configuration, low-energy consumption, and high-speed switching performance. Because of the above advantages, the solid-state relay can be successfully incorporated in a small device, such as an automatic test equipment for testing LSI chips, for example. When utilized for the measurement of this kind, the relay is designed to provide a series of output signal as a testing signal. As the frequency of the output signal becomes higher, the relay is required to have a lower output capacitance developed across output terminals of the relay during off-periods of the output signal, i.e., the periods in which the output terminals are in non-conductive condition, in addition to minimizing on-state resistance between the output terminals during on-periods of the output signal. The output capacitance is the sum of a drain-source capacitance and a gate-drain capacitance at the non-conductive condition of the output terminals of the relay.
Japanese Patent Laid-Open Publication No. 9-312392 discloses a solid state relay which utilizes LDMOSFETs as switching elements in an attempt to reduce the output capacitance. The LDMOSFET has structure in which a well region and a drift region are diffused in the top surface of a silicon layer with a source region being diffused within a confine of the well region and with a drain region being diffused within a confine of the drift region. However, since the drift region and the well region are formed in the top surface of the silicon layer, there is formed a P-N interface of extended area including the bottoms of the drift region and the well region. The P-N interface of such enlarged area is responsible for increasing a capacitance between the source and drain of LDMOSFET. Accordingly, the LDMOSFET of this structure is not satisfactory for minimizing the output capacitance between the output terminals of the relay.
The present invention has been accomplished in view of the above insufficiency to provide a solid state relay which is capable of minimizing an output capacitance across output terminals of the relay, while retaining a low on-state resistance across the output terminals. The solid-state relay in accordance with the present invention comprises a control unit which gives an electrical energy upon receipt of an input signal and a pair of LDMOSFETs (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistors) mounted on a supporting plate of electrically conductive material. LDMOSFETs are arranged in circuit with individual gates commonly coupled to receive the electrical energy from the control unit so as to be driven thereby to turn on and off. Sources of LDMOSFETs are connected to each other in a series fashion so as to have individual drains connected to the output terminals, respectively. Each LDMOSFET is configured to have a silicon layer of a first conductive type, a drain region of the first conductive type diffused in the top surface of the silicon layer, a well region of a second conductive type diffused in the silicon layer in a laterally spaced relation from the drain region, and a source region of the first conductive type diffused within the well region to define a channel extending between the source region and a confronting edge of the well region along the top surface of the silicon layer. The source region and the drain region define respectively the source and drain of LDMOSFET. Drain and source electrodes are placed respectively over the drain and source regions in electrically connected relation thereto. A gate electrode is connected to a gate layer of an electrically conductive material which is placed over the channel through a dielectric layer and which defines the gate of LDMOSFET. A characterizing feature of the solid-solid state relay resides in that each LDMOSFET is of an SOI (Silicon-On-Insulator) structure composed of a silicon substrate placed on said supporting plate, a buried oxide layer on the silicon substrate, and the silicon layer on the buried oxide layer, and that the well region extends the full depth of the silicon layer to have a bottom abutted against said buried oxide layer.
Since the well region is diffused over the full depth of the silicon layer to have its bottom abutted against the buried oxide layer, the well region of the second conductive type forms with the silicon layer of the first conductive type a P-N interface only at a small portion adjacent the channel. That is, only a side boundary of the well region laterally confronting the drain region forms the P-N interface. Because of this reduced P-N interface and also because of the buried oxide layer exhibiting much lower capacitance than the silicon layer, it is possible to greatly reduce a drain-source capacitance for minimizing the output capacitance of the relay in the non-conductive condition. Also the reduced P-N interface area can reduce a leak current at the non-conducting condition of the output terminals. Moreover, the SOI structure can assure sufficient flexibility for mounting the LDMOSFET on the supporting plate, either with one of the drain and source being electrically connected to the supporting plate or being electrically isolated, in accordance with particular demands.
One of the source region and the drain region is configured to surround the other within a plane of the silicon layer. This surrounding arrangement enables the source region to confront the drain region over a prolonged line in the plane of the silicon layer, thereby reducing an on-state resistance between the output terminals of the relay. Accordingly, the relay can enjoy an optimum combination of the low output capacitance and the low on-state resistance. Although there exists a factual relation that the smaller the on-state resistance is, the greater the output capacitance becomes, the above structure of reducing the P-N interface area is most effective to minimize the output capacitance when the on-state resistance is required to be reduced to an acceptable extent. Preferably, the source region is configured to surround the drain region.
Further, the present invention envisages to minimize an effect of developing an additional capacitance between the source and the drain or between the gate and the source owing to the presence of the buried oxide layer, particularly when the single supporting plate mounting the pair of LDMOSFETs is utilized to electrically interconnect the sources of LDMOSFETs or when the two separate supporting plates each mounting the LDMOSFET are each utilized to interconnect the drain and the output terminal of the relay. In order to facilitate the recognition of several advantages of the present invention, there are introduced terms, xe2x80x9cprimary drain-source capacitancexe2x80x9d and xe2x80x9csecondary drain-source capacitancexe2x80x9d. The primary drain-source capacitance is utilized to denote the capacitance substantially developed through a portion of the silicon layer between drain region and source region, while the secondary drain-source capacitance is for an additional capacitance developed through the buried oxide layer in a vertical path from the source region to the supporting plate kept at the same potential of the drain or from the drain region to the supporting plate at the same potential of the source.
The silicon layer has a peripheral zone located laterally outwardly of the well region and electrically isolated from the drain region by the well region. It is preferred to electrically connect the peripheral zone and the drain commonly to the supporting plate. Thus, the peripheral zone around the well region can be kept at the same potential as the drain region, thereby eliminating an additional path of developing a capacitance through the buried oxide layer between the peripheral zone and the silicon substrate. Otherwise, the additional path would add a capacitance in parallel with the secondary drain-source capacitance inevitably developed between the bottom of the well region and the supporting plate through the buried oxide layer, thereby bringing about unduly large parallel connected capacitance between the source and drain.
In addition, a separator ring of dielectric material may be formed in the peripheral zone to surround closely the well region in such a manner as to electrically isolate the well region from the peripheral zone. Thus, it is possible to prevent an unduly high capacitance from developing between the well region and the peripheral zone, thereby minimizing the overall drain-source capacitance when the drain and the peripheral zone are electrically connected to the supporting plate.
Further, at least one separated land of the second conductive type may be diffused in the silicon layer outwardly of the well region in a spaced relation therefrom. At least one of the source electrode and the gate electrode extends over the separated land in a spaced relation thereto from the corresponding one of the source and the channel to form a wiring pad for wiring connection to a complementary circuit element. Also with this arrangement of providing the wiring pad over the separated land, it is possible to reduce an additional capacitance resulting from the provision of the pad and correspondingly minimize the overall source-drain or gate-drain capacitance.
Alternatively, at least one separated land of the first conductive type may be diffused within the well region to extend the full depth of the silicon layer in an electrically isolated relation from the source region. At least one of the source electrode and the gate electrode extends over the separator region in a spaced relation thereto from the corresponding one of the source and the channel to form a wiring pad for wiring connection to a complementary circuit element for the purpose of minimizing the in order to minimize the overall source-drain or gate-drain capacitance in the manner as discussed in the above.
When the drain region is configured to surround the well region and the supporting plate is utilized to electrically interconnect the sources of the two LDMOSFETs, it is preferred to connect a peripheral zone outwardly of the drain region electrically to the supporting plate. Thus, the peripheral zone outwardly of the drain region can develop no additional capacitance through the corresponding portion of the buried oxide layer, thereby minimizing the source-drain capacitance. Also in this structure, a dielectric separator ring may be utilized to surround closely the drain region. The separator ring is formed in the silicon layer to isolate the drain region from the peripheral zone of the silicon layer, in order to give an optimum dielectric strength between the drain and the source, in addition to minimizing the source-drain capacitance.
When the source or drain is electrically connected to the supporting plate, the silicon substrate is preferably formed with a cavity or recess extending in correspondence to the drain region or well region in order to further reduce the drain-source capacitance by the intervention of the cavity or recess between the source or drain region and the supporting plate.
In a further version, there is formed an electrically insulator stud which extends from the buried oxide layer through a center of the drain region to project on the top surface of the silicon layer in such a manner as to expose the drain region in an annular shape around the stud. The associated drain electrode is arranged to extend over the insulator stud with a peripheral zone of the drain electrode being electrically connected to the drain region of the annular shape. The combination of the insulator stud and drain electrode can effectively reduce the drain-source capacitance while assuring sufficient dimensions for the drain electrode.
The silicon substrate may comprise a pair of semiconductor stratums of opposite conductive types which develops a depletion layer at the P-N interface therebetween. The resulting depletion layer gives an additional capacitance which is added in series capative connection with the secondary drain-source capacitance of the buried oxide layer, thereby reducing the overall drain-source capacitance.
The relay of the present invention may further include a dielectric layer on a bottom of the silicon substrate opposite of said buried oxide layer in order to further reduce the secondary drain-source capacitance.
In a further version of the present invention, it is contemplated to integrate the two LDMOSFET in a single device structure. In this structure, the well region are formed in the single silicon layer over the full depth thereof in such a manner as to form therein a laterally isolated pair of first and second active zones. Diffused in the well region is a pair of first and second source regions which surround respectively the first and second active zones and define first and second channels extending within the well regions from the first and second source regions to confronting boundaries of the first and second active zones, respectively. First and second drain regions are diffused respectively within the first and second active zone so as to be isolated from each other by the well region. First and second drain electrodes are placed respectively on the first and second drain regions in an electrical connecting relationship therewith. At least one gate electrode is electrically connected to first and second gate layers which are placed over the first and second channels respectively through dielectric layers and define first and second gates of the two LDMOSFETs, respectively. A common source electrode is provided to bridge over the first and second source regions and is electrically connected thereto. The silicon substrate carrying the silicon layer through the buried oxide layer is mounted on the supporting frame with the output terminals being electrically connected respectively to the first and second drains. Thus, the two LDMOSFETs can be realized in the single device structure and can be easily assembled into the solid-state relay, while retaining to minimize drain-source capacitance.
In this structure of realizing the two LDMOSFETs commonly in the single silicon layer, the supporting plate may be electrically isolated from the common source as well as from the first and second drains, and the output terminals are formed separately from the supporting plate for electrically connection with the first and second drains.